(a) Fields of the Invention
The present invention relates to semiconductor integrated circuit devices. In particular, the present invention relates to semiconductor integrated circuit devices which have a circuit for preventing electrostatic breakdown and which supply fixed signals with low and high levels to another circuit.
(b) Description of Related Art
In a recent field of fabrication process of semiconductor integrated circuit devices, technologies for miniaturization and high packing density of the devices have been developed, and thus high integration thereof has been proceeding. Accompanied with this trend, the semiconductor integrated circuit devices become sensitive to damages caused by electrostatic discharges. For example, the possibility is growing that a surge entering from an external connection terminal breaks elements of an input circuit, an output circuit, an input and output circuit, or an internal circuit and therefore performances of the elements are degraded. To prevent this, a protection circuit additionally attached to the external connection terminal and protecting from the surge the input circuit, the output circuit, the input and output circuit, or the internal circuit.
FIGS. 5 and 6 are diagrams showing conventional configurations of electric circuits for supplying fixed signals with low and high levels to another circuit. A semiconductor integrated circuit shown in FIG. 5 is provided with an NMIS (Metal-Insulator-Semiconductor) transistor 103 and a power clamp circuit for electrostatic discharge protection (referred hereinafter to as an ESD protection power clamp circuit) 104. In this configuration, a gate of the NMIS transistor 103 is directly connected to a power line 101. When the power line 101 is at a high level, the NMIS transistor 103 is turned on. In response to this, a low-level output line 105 becomes a low level and supplies a fixed low-level signal to another circuit.
A semiconductor integrated circuit shown in FIG. 6 is provided with a PMIS transistor 106 and an ESD protection power clamp circuit 104. In this configuration, a gate of the PMIS transistor 106 is directly connected to a ground line 102. When the ground line 102 is at a low level, the PMIS transistor 106 is turned on. In response to this, a high-level output line 105 becomes a high level and supplies a fixed high-level signal to another circuit. The ESD protection power clamp circuits 104 shown in FIGS. 5 and 6 are off during normal operations. However, for example, if a surge due to an electrostatic discharge is applied to the power line 101, the ESD protection power clamp circuit 104 is clamped to pass the surge to the ground line (see, for example, Japanese Unexamined Patent Publication No. H07-86906).
While the ESD protection power clamp circuit 104 passes the surge to the ground line 102, however, the potential of the power line 101 rises and a potential difference is generated between a substrate and the gate of the NMIS transistor 103 or the PMIS transistor 106. If this potential difference is above the breakdown voltage of the gate insulating film of the NMIS transistor 103 or the PMIS transistor 106, the gate insulating film is broken down. Once the gate insulating film is broken down, this circuit cannot supply a fixed signal to another circuit.
In addition, recently, accompanied with miniaturization of fabrication processes, a gate insulating film has been increasingly thinned. As a consequence of this, the breakdown voltage of the film has been lowering. Also by this trend, the gate insulating film has come to be broken down more easily.
In order to prevent generation of a potential between a gate and a substrate, an approach is conceivable in which the dimensions of a transistor of the ESD protection power clamp circuit are increased to enhance the performance of the circuit. However, with this approach, the area of the ESD protection power clamp circuit is increased to enlarge the chip size. Consequently, the formed device is against the demands of miniaturization.